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74F162A Synchronous Presettable BCD Decade Counter
April 1988 Revised January 2004
74F162A Synchronous Presettable BCD Decade Counter
General Description
The 74F162A is a high-speed synchronous decade counter operating in the BCD (8421) sequence. They are synchronously presettable for applications in programmable dividers. The F162A has a Synchronous Reset input that overrides counting and parallel loading and allows all outputs to be simultaneously reset on the rising edge of the clock. The F162A is a high speed version of the F162.
Features
s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 120 MHz
Ordering Code:
Order Number 74F162ASC 74F162APC Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Logic Symbols
74F162A 74F162A
74F162A
(c) 2004 Fairchild Semiconductor Corporation
DS009485
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74F162A
Unit Loading/Fan Out
U.L. Pin Names CEP CET CP SR P0-P3 PE Q0-Q3 TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output 1.0/1.0 1.0/2.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/2.0 50/33.3 50/33.3 Input IIH/IIL HIGH/LOW Output IOH/IOL 20 A/-0.6 mA 20 A/-1.2 mA 20 A/-0.6 mA 20 A/-1.2 mA 20 A/-0.6 mA 20 A/-1.2 mA
-1 mA/20 mA -1 mA/20 mA
Functional Description
The 74F162A count modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-toHIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: synchronous reset, parallel load, count-up and hold. Four control inputs-- Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)--determine the mode of operation, as shown in the Mode Select Table. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and SR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The F162A uses D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 9. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the F568 datasheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the F162A decade counters, the TC output is fully decoded and can only be HIGH in state 9. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the State Diagram. Logic Equations: Count Enable = CEP x CET x PE TC = Q0 x Q 1x Q 2 x Q3 x CET
Mode Select Table
SR L H H H H PE X L H H H CET CEP X X H L X X X H X L Action on the Rising Clock Edge () Reset (Clear) Load (Pn Qn) Count (Increment) No Change (Hold) No Change (Hold)
State Diagram
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
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74F162A
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F162A
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C
+4.5V to +5.5V
-0.5V to VCC -0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current IIL IOS ICC Input LOW Current Output Short-Circuit Current Power Supply Current -60 37 4.75 3.75 -0.6 -1.2 -150 55 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A mA mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (CP, CEP,Pn, MR (F160A)) VIN = 0.5V (CET, SR (F162A), PE) VOUT = 0V VO = HIGH
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74F162A
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Count Frequency Propagation Delay, Count CP to Qn (PE Input HIGH) Propagation Delay, Load CP to Qn (PE Input LOW) Propagation Delay CP to TC Propagation Delay CET to TC 90 3.5 3.5 4.0 4.0 5.0 5.0 2.5 2.5 VCC = +5.0V CL = 50 pF Typ 120 5.5 7.5 6.0 6.0 10.0 10.0 4.5 4.5 7.5 10.0 8.5 8.5 14.0 14.0 7.5 7.5 Max TA = -55C to +125C VCC = +5.0V CL = 50 pF Min 75 3.5 3.5 4.0 4.0 5.0 5.0 2.5 2.5 9.0 11.5 10.0 10.0 16.5 15.5 9.0 9.0 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 80 3.5 3.5 4.0 4.0 5.0 5.0 2.5 2.5 8.5 11.0 9.5 9.5 15.0 15.0 8.5 8.5 Max MHz ns ns ns ns Units
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(H) tW(L) Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE or SR to CP Hold Time, HIGH or LOW PE or SR to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW 5.0 5.0 2.0 2.0 11.0 8.5 2.0 0 11.0 5.0 0 0 5.0 5.0 4.0 6.0 2.5 2.5 13.5 10.5 2.0 0 13.0 6.0 0 0 5.0 5.0 5.0 8.0 Max TA = -55C to +125C VCC = +5.0V Min Max TA = 0C to +70C VCC = +5.0V Min 5.0 5.0 2.0 2.0 11.5 9.5 2.0 0 11.5 5.0 0 0 5.0 5.0 4.0 7.0 ns ns ns ns ns Max Units
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74F162A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
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74F162A Synchronous Presettable BCD Decade Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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